HIGH VOLTAGE GENERATION CIRCUIT AND METHOD FOR REDUCING RIPPLE OF OUTPUT VOLTAGE

摘要

A high voltage generation circuit for reducing ripple of an output voltage and a method thereof are provided to provide a stable high voltage with reduced ripple, by controlling enable period of a clock signal controlling charge pumping for generating the high voltage. A delay circuit(330) generates a number of delay clock signals having predetermined delay time on the basis of a clock signal. A number of pumps(340-344) generate a high voltage by performing charge pumping operation in response to a corresponding delayed clock signal. The high voltage generation circuit further comprises a regulator(310) and a clock generator(320). The regulator generates an enable signal on the basis of the voltage level of the high voltage. The clock generator generates the clock signal having variable enable period in response to the enable signal and an external clock signal.