发明名称 INTEGRIERTE SCHALTUNG UND VERFAHREN ZUR ZEITSCHLITZ-ZUTEILUNG
摘要 An integrated circuit comprising a plurality of processing modules (M, S; IP) and a network (N) arranged for coupling said modules (M, S; IP) is provided. Said integrated circuit further comprises a plurality of network interfaces (NI) each being coupled between one of said processing modules (M, S; IP) and said network (N). Said network (N) comprises a plurality of routers (R) coupled via network links (L) to adjacent routers (R). Said processing modules (M, S; IP) communicate between each other over connections using connection paths (C1-C12) through the network (N), wherein each of said connection paths (C1-C12) employ at least one network link (L) for a required number of time slots. At least one time slot allocating unit (SA) is provided for computing a link weight factor for at least one network link (L) in said connection path (C1-C12) as a function of at least one connection requirement for said at least one network link (L), for computing a connection path weight factor for at least one connection path (C1-C12) as a function of the computed link weight factor of at least one network link (L) in said connection path (C1-C12), and for allocating time slots to said network links (L) according to the computed connection path weight factors.
申请公布号 AT403314(T) 申请公布日期 2008.08.15
申请号 AT20050709078T 申请日期 2005.03.23
申请人 KONINKLIJKE PHILIPS ELECTRONICS N.V. 发明人 RADULESCU, ANDREI
分类号 H04L12/911;H04L12/725 主分类号 H04L12/911
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