发明名称 BUS INTERFACE CIRCUIT AND INFORMATION PROCESSOR
摘要 PROBLEM TO BE SOLVED: To provide a technique capable of improving use efficiency of a bus. SOLUTION: An internal processing module 311 detects the head of a first period repeated at a constant frequency. The internal processing module 311 outputs, when the head of the first period visits first after receipt of a bus use permission signal, the address of data that is a reading object to the bus 100 within a second period shorter than the first period. The module 311 inputs, after a lapse of a third period calculated by multiplying the period by a predetermined positive integer, data corresponding to the address which is output by a slave device to the bus 100 within a fourth period after reduction of the second period from the period successively to the third period. COPYRIGHT: (C)2008,JPO&INPIT
申请公布号 JP2008186093(A) 申请公布日期 2008.08.14
申请号 JP20070016989 申请日期 2007.01.26
申请人 FUJI XEROX CO LTD 发明人 TOI TETSUYA
分类号 G06F13/362 主分类号 G06F13/362
代理机构 代理人
主权项
地址