发明名称 WAFER FOR EVALUATING PACKAGE OF SEMICONDUCTOR CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a wafer for evaluating a package of a semiconductor circuit that allows wire-bonding evaluation and electric-characteristics evaluation, makes it possible to obtain evaluation chips having different sizes from the same wafer, and allows evaluation of the whole evaluation chip. SOLUTION: The wafer 1 is composed as follows. Both a plurality of wire-bonding evaluation pads 5a-5h and a plurality of electric-characteristics evaluation pads 4a-4d are provided along the four sides. A plurality of unit chips 2, respectively having a sufficient size for forming a semiconductor circuit element, is formed. The wafer is cut out for each of a desired number of unit chips 2 and stored inside a package as an evaluation target in order to electrically evaluate effects because of the package. Wire-bonding evaluation wirings 6a-6d, 7a-7d connected to the wire-bonding evaluation pads 5a-5h and electric-characteristics evaluation wirings 8a-8h, connected to the electric-characteristics evaluation pads 4a-4d, in the entire area of the wafer 1 are provided in the wafer 1 so as to be insulated from each other. COPYRIGHT: (C)2008,JPO&INPIT
申请公布号 JP2008187073(A) 申请公布日期 2008.08.14
申请号 JP20070020586 申请日期 2007.01.31
申请人 SEIKO NPC CORP 发明人 KANEKO KOJI;OTA KAZUNORI
分类号 H01L21/66;H01L21/822;H01L27/04 主分类号 H01L21/66
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