发明名称 12c Slave/Master Interface Enhancement Using State Machines
摘要 Consistent with one example embodiment, communications systems, using a serial data transfer bus ( 125 ) having a serial data line and a clock line used to implement a communications protocol, incorporate enhanced slave/master interfacing on an I2C bus using state machines. The communications system includes a first and second state-machine ( 150,160 ) responsive to the rising edge of the clock signal ( 134 ), and a third state-machine, distinctly operational from the first and second state-machine, responsive to the falling edge of the clock signal. One of the first state-machine and the second state-machine conform to write states of the communications protocol, and the other of the first state-machine and the second state-machine ( 170 ) conform to read states of the communications protocol.
申请公布号 US2008195783(A1) 申请公布日期 2008.08.14
申请号 US20060913067 申请日期 2006.05.01
申请人 NXP B.V. 发明人 DESHPANDE AMRITA
分类号 G06F13/18;G06F13/42 主分类号 G06F13/18
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