| 摘要 |
A regulator circuit for efficiently and accurately outputting a target voltage with a simple circuit configuration. The regulator circuit includes an output circuit, a comparator, a counter block, a latch block, and a decoder block. When the target voltage is applied to an output terminal of the output circuit, the output circuit supplies the comparator with feedback voltage. Further, the feedback signal is provided to the counter block. The counter block performs counting in correspondence with the feedback signal. The latch block holds the signal acquired from the counter block and provides the held signal to the decoder block. The decoder block supplies the comparator with reference voltage. The comparator compares the reference voltage and the feedback voltage and controls the counting.
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