发明名称 |
METAL GATES WITH LOW CHARGE TRAPPING AND ENHANCED DIELECTRIC RELIABILITY CHARACTERISTICS FOR HIGH-k GATE DIELECTRIC STACKS |
摘要 |
A multilayered gate stack having improved reliability (i.e., low charge trapping and gate leakage degradation) is provided. The inventive multilayered gate stack includes, from bottom to top, a metal nitrogen-containing layer located on a surface of a high-k gate dielectric and Si-containing conductor located directly on a surface of the metal nitrogen-containing layer. The improved reliability is achieved by utilizing a metal nitrogen-containing layer having a compositional ratio of metal to nitrogen of less than 1.1. The inventive gate stack can be useful as an element of a complementary metal oxide semiconductor (CMOS). The present invention also provides a method of fabricating such a gate stack in which the process conditions of a sputtering process are varied to control the ratio of metal and nitrogen within the sputter deposited layer.
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申请公布号 |
US2008191292(A1) |
申请公布日期 |
2008.08.14 |
申请号 |
US20070673901 |
申请日期 |
2007.02.12 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
CALLEGARI ALESSANDRO C.;CHUDZIK MICHAEL P.;LINDER BARRY P.;MO RENEE T.;NARAYANAN VIJAY;PARK DAE-GYU;PARUCHURI VAMSI K.;ZAFAR SUFI |
分类号 |
H01L29/49;H01L21/3205 |
主分类号 |
H01L29/49 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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