| 摘要 |
A clock control circuit includes a first signal generation block for outputting a first internal clock signal, which is enabled after delay of a first time from a rising edge of a first input clock signal and has a high level pulse width shorter by a second time than a high level pulse width of the first input clock signal, and a second signal generation block for outputting a second internal clock signal, which is enabled after delay of the first time from a rising edge of a second input clock signal and has a high level pulse width shorter by the second time than a high level pulse width of the second input clock signal.
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