| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit designing device capable of arranging cells on the shared clock route of a plurality of clock signals at positions by which a clock propagation delay time is made to be shortest. SOLUTION: The multiple clock input cell extracting part 11 of the semiconductor integrated circuit designing device 1 extracts the cell where the plurality of clock signals are inputted. A shared clock route cell extracting part 12 extracts the cells existing in the multiple clock shared clock route for transmitting the output of the multiple clock input cell. A cell destination position calculating part 13 calculates the destination positions of the multiple clock input cell and the shared clock route cells, capable of shortening the propagation delay time of the shared clock route, based on the cell arrangement position information of the shared clock route cells. A cell arrangement position change part 14 changes the arrangement positions of the multiple clock input cell and the shared clock route cells into the calculated movement destination positions. COPYRIGHT: (C)2008,JPO&INPIT
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