METHOD AND APPARATUS FOR CORRECTING DUTY CYCLE ERROR IN A CLOCK DISTRIBUTION NETWORK
摘要
<p>A clock distribution network for distributing a repetitive timing signal throughout an integrated circuit, the timing signal being within a range of frequencies about a first frequency, includes multiple buffer circuits and at least one conductive segment connecting one of the buffers to another of the buffers. The conductive segment has a length selected so as to be less than a quarter-wave resonance length of the conductive segment at the first frequency to thereby achieve duty cycle correction.</p>
申请公布号
WO2008097309(A1)
申请公布日期
2008.08.14
申请号
WO2007US61642
申请日期
2007.02.06
申请人
INTERNATIONAL BUSINESS MACHINES CORPORTION;HWANG, CHARLIE, CHORNGLII;RESTLE, PHILLIP, JOHN;THOMSON, MICHAEL, GEORGE, ROBERT
发明人
HWANG, CHARLIE, CHORNGLII;RESTLE, PHILLIP, JOHN;THOMSON, MICHAEL, GEORGE, ROBERT