发明名称 |
Buffer circuit having electrostatic discharge protection |
摘要 |
The pull-up and pulldown sections in each output buffer are fed from separate power rails 40,46;42,48;44,50 so that a positive ESD impulse on any I/O pad cannot couple through the pull-up circuit MP10 to the gate of the pull-down cascode device MNA and cause gate voltage induced current crfowding (GVICC). The pulldown circuit in each block shares a common supply with the pullup circuits in adjacent blocks. Positive ESD impulses on the I/O pad may be discharged to Earth by parasitic lateral NPN transistors associated with the pulldown transistors (figure 2). |
申请公布号 |
GB2445327(B) |
申请公布日期 |
2008.08.13 |
申请号 |
GB20080006766 |
申请日期 |
2004.12.30 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD |
发明人 |
CHAN-HEE JEON;BONG-JAE KWON;EUN-KYOUNG KWON |
分类号 |
H01L27/02;H01L27/04;H03K19/003;H03K19/0185 |
主分类号 |
H01L27/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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