发明名称 Isolation structure configurations for modifying stresses in semiconductor devices
摘要 An apparatus and methods for modifying isolation structure configurations for MOS devices to either induce or reduce tensile and/or compressive stresses on an active area of the MOS devices. The isolation structure configurations according to the present invention include the use of low-modulus and high-modulus, dielectric materials, as well as, tensile stress-inducing and compressive stress-inducing, dielectric materials, and further includes altering the depth of the isolation structure and methods for modifying isolation structure configurations, such as trench depth and isolation materials used, to modify (i.e., to either induce or reduce) tensile and/or compressive stresses on an active area of a semiconductor device.
申请公布号 US7411269(B2) 申请公布日期 2008.08.12
申请号 US20050091967 申请日期 2005.03.28
申请人 发明人
分类号 H01L29/72;H01L21/762;H01L29/00;H01L29/76;H01L31/113;H01L31/119 主分类号 H01L29/72
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