| 摘要 |
A broadcaster, system, and method for reducing test data volume and test application time in an ATE (automatic test equipment) in a scan-based integrated circuit. The scan-based integrated circuit contains multiple scan chains, each scan chain comprising multiple scan cells coupled in series. The broadcaster is a combinational logic network coupled to an optional virtual scan controller and an optional scan connector. The virtual scan controller controls the operation of the broadcaster. The system transmits virtual scan patterns stored in the ATE and generates broadcast scan patterns through the broadcaster for testing manufacturing faults in the scan-based integrated circuit. The number of scan chains that can be supported by the ATE is significantly increased. Methods are further proposed to reorder scan cells in selected scan chains, to generate the broadcast scan patterns and virtual scan patterns, and to synthesize the broadcaster and a compactor in the scan-based integrated circuit. The scan architecture used can also be random access scan based, where the integrated circuit comprises an array of random access scan (RAS) cells that are randomly and uniquely addressable. In random access scan, test patterns can be applied by selectively updating RAS cells and test responses can be observed through a direct read-out process. Eliminating the shifting process inherent in serial scan, random access scan produces much lower test power dissipation than serial scan.
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