Apparatus and method for verifying an integrated circuit pattern

摘要

A first generator section generates a tolerance data corresponding to a target pattern set based on a design data of a semiconductor device. A second generator section generates an image data of a semi-conductor device pattern formed based on the target pattern. An extraction section extracts a contour data of the pattern from the image data supplied from the second generator section. A data synthesizing section is supplied with the tolerance data supplied from the second generator section and the contour data supplied from the extraction section. The data synthesizing section overlaps the tolerance data with the contour data.