| 摘要 |
<p>A wafer level system-in-package and a method for manufacturing the same are provided to significantly improve electric characteristics of a system by reducing a wire length with a logic device and a passive device. A method for manufacturing a wafer level system-in-package includes: forming a first rearrangement conductive layer(240) on an upper surface of a memory(200); forming a through hole(260) penetrating the memory; filling the through hole with a conductive material; forming a second rearrangement conductive layer(280) on a lower surface of the memory; and electrically connecting at least one system semiconductor device to the upper surface of the memory; and mounting at least one passive device on the upper surface of the memory.</p> |
