ON-CHIP TESTING

摘要

A system-on-chip (SoC) comprises a processor (10), a system bus (11), and embedded cores (4), and a dedicated test controller (3) connected to the system bus (11) by a system bus interface (12). The test controller (3) reuses the system bus (11) to route structural test vectors to the cores to implement Test Access Mechanisms (TAMs). The test controller (3) treats external automatic test equipment as a memory and autonomously performs on-chip testing while retrieving data from the automatic test equipment. The test controller (3) interfaces with the cores (4) via wrappers (6), each of which has an instruction register for controlling the test controller access. The system bus master is the general purpose processor (10). The test controller (3) and the core wrappers (4) allow concurrent testing and the test controller (3) controls a scan-chain testing technique using scan chains in the cores (4) to isolate semiconductor faults through a test wrapper.