| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a data transfer circuit capable of transferring data even in a blanking period and optimizing the frequency of a transfer clock. <P>SOLUTION: A comparator circuit 13 compares the counted results of a counter (#1) 11 and a counter (#2) 12 respectively, and outputs UP signals when the counter (#1) 11 is faster and DOWN signals when the counter (#2) 12 is fastener respectively to a PLL 14. The PLL 14 adjusts and outputs a master clock MCLK2 on the side of the counter (#2) 12 corresponding to the UP/DOWN signals from the comparator circuit 13. A buffer 15 uses control signals outputted from the counter (#1) 11 and the counter (#2) 12, inputs the data DATA1 of a device needing the blanking period to be stored and outputs the data DATA2 of the device not needing the blanking period. <P>COPYRIGHT: (C)2008,JPO&INPIT</p> |
