| 摘要 |
<P>PROBLEM TO BE SOLVED: To reduce the number of data signals inputted to a latch circuit of a driver. <P>SOLUTION: An input section 11a of the driver is provided with a data selection circuit 21, a shift resister 22, and a latch section 23. The data selection circuit 21 inputs a data signal DO, a clock signal CLK, and a reset signal RST, outputs the data signal DO latched at the rising edge of the clock signal CLK as a data signal DSa, and outputs the data signal DO latched at the trailing edge of the clock signal CLK as a data signal DSb. A shift register 22 inputs a start pulse signal ST, the clock signal CLK, and the reset signal RST, outputs the data signal DSa, and the first data latch signal for latching the data of the DSb to the latch section 23 after the start pulse signal ST changes from a "High" level to a "Low" level, then successively outputs the data latch signal to the latch section 23 for every one period of the clock signal CLK. <P>COPYRIGHT: (C)2008,JPO&INPIT |
