| 摘要 |
PROBLEM TO BE SOLVED: To provide a pipeline type ADC which has small influence of errors of respective stages on linearity of analog-to-digital conversion and also has small influence of a missing code. SOLUTION: The analog-to-digital converter (ADC) 80 comprises a plurality of analog-to-digital conversion stages 90, 92, 94, and 96, correction logics 100, 102, and 104 recursively correcting conversion errors, and a code range arithmetic logic 82 which calculates an upper-limit value and a lower-limit value of digital values that the ADC 80 can output. The correction logics 100, 102, and 104 include a circuit for receiving an analog input signal from a previous stage, a circuit for receiving a digital input signal from a previous stage, a converting circuit for quantizing the analog input signal, and a correcting circuit for generating a correction signal having a value corresponding to the digital input signal. The code range arithmetic logic 82 uses correction values of respective stages and finds the upper-limit value and lower-limit value through operations comprising an adding and a shifting operation. COPYRIGHT: (C)2008,JPO&INPIT
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