| 摘要 |
Serial data in the presence of jitter is captured by clocking the data into several different shift registers, each driven by a clock of the correct frequency but having different phases. In keeping with certain system standards, a periodic synchronization frame is transmitted which is recognizable by its known content. Upon the conclusion of each synchronization frame the content of each shift register is compared against the expected content. The pattern of successful and failed comparisons is examined (say, applied to a look-up table) and the shift register having the optimum phase clock is selected. Between synchronization frames the selected sift register continues to be clocked by that phase and receive data, (as may be the other shift registers by their respective phases), but only that selected shift register is used to act as the receiver and transfer its data to some downstream using mechanism.
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