发明名称 |
Address Translation Method and Apparatus |
摘要 |
Address translation performance within a processor is improved by identifying an address that causes a boundary crossing between different pages in memory and linking address translation information associated with both memory pages. According to one embodiment of a processor, the processor comprises circuitry configured to recognize an access to a memory region crossing a page boundary between first and second memory pages. The circuitry is also configured to link address translation information associated with the first and second memory pages. Thus, responsive to a subsequent access the same memory region, the address translation information associated with the first and second memory pages is retrievable based on a single address translation.
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申请公布号 |
US2008189506(A1) |
申请公布日期 |
2008.08.07 |
申请号 |
US20070672066 |
申请日期 |
2007.02.07 |
申请人 |
KOPEC BRIAN JOSEPH;AUGSBURG VICTOR ROBERTS;DIEFFENDERFER JAMES NORRIS;SARTORIUS THOMAS ANDREW |
发明人 |
KOPEC BRIAN JOSEPH;AUGSBURG VICTOR ROBERTS;DIEFFENDERFER JAMES NORRIS;SARTORIUS THOMAS ANDREW |
分类号 |
G06F12/00 |
主分类号 |
G06F12/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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