发明名称 CIRCUIT AND METHOD FOR REDUCING PIN COUNT OF CHIP
摘要 A configured setting circuit and method thereof is disclosed. The configured setting circuit includes a multi-phase clock generator, a plurality of terminals, and a decision circuit. The multi-phase clock generator generates a plurality of multi-phase signals with different phases to be outputted via the terminals. The decision circuit detects a phase difference between the input signal and the reference signal and outputs a configuration data according to the phase difference between the input signal and the reference signal.
申请公布号 US2008186074(A1) 申请公布日期 2008.08.07
申请号 US20080025687 申请日期 2008.02.04
申请人 YEH MING-YUH 发明人 YEH MING-YUH
分类号 G06F1/04;H03K3/00 主分类号 G06F1/04
代理机构 代理人
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