发明名称 Method of manufacturing wafer-level chip-size package and molding apparatus used in the method
摘要 Provided are a method of manufacturing wafer-level chip-size packages and a molding apparatus suitable for practicing the method whereby a semiconductor wafer having a plurality of semiconductor chips formed thereon may be encapsulated. The semiconductor wafer, typically with a plurality of conductive bumps extending from the semiconductor chips, will be placed in a cavity formed between upper and lower molds. Injection molding of an encapsulant composition or compression molding of encapsulant sheets may then be used to apply encapsulating layers to the upper and lower surfaces of the semiconductor wafer in a substantially simultaneous manner, thereby reducing the likelihood of warping and mechanical damage to the semiconductor wafer. The wafer-level chip-size packages can then be separated from the encapsulated semiconductor wafer.
申请公布号 US2008187613(A1) 申请公布日期 2008.08.07
申请号 US20080078638 申请日期 2008.04.02
申请人 YOON TAE-SUNG 发明人 YOON TAE-SUNG
分类号 B29C45/03;H01L23/12;B29C43/36;B29C45/14;H01L21/56;H01L23/31 主分类号 B29C45/03
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