发明名称 TRI-STATING A PHASE LOCKED LOOP TO CONSERVE POWER
摘要 In a system with an intermittently operating radio, the frequency of which is controlled by a Phase Locked Loop (PLL), a method and system for reducing the power consumed by the PLL by tri-stating the control capacitor in the PLL after the PLL has stabilized at a design frequency. After the capacitor is stabilized, power to some of the components in the PLL is reduced.
申请公布号 KR20080072632(A) 申请公布日期 2008.08.06
申请号 KR20087007212 申请日期 2006.09.12
申请人 CYPRESS SEMICONDUCTOR CORPORATION 发明人 GEHRING MARK R.;MOYAL NATHAN
分类号 H04B1/06;H04B7/00 主分类号 H04B1/06
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