| 摘要 |
The method involves loading a dielectric gate (A) of a FET (T1) at a predefined test voltage (VP), and setting high impedance to the gate of the transistor. Ageing of the gate of the transistor is measured using loading or unloading time by an ageing measuring circuit (100) for passing from the define test voltage to a reference voltage (VREF). The measured ageing value is stored in a non volatile memory e.g. flash memory. An operation bias voltage of the transistor is determined based on the measured ageing and the applied test voltage. |
