发明名称 Method and device for verifying output signals of an integrated circuit
摘要 A system and method for testing an integrated circuit is provided. In one embodiment, a method includes comparing the signal level of the output signal of the integrated circuit to the signal level of a reference signal, wherein a comparison signal is output, which has a first or a second value depending on whether the actual signal level of the output signal is above or below the actual signal level of the reference signal; determining the value of the comparison signal at a certain time; evaluating the value of the comparison signal determined at the time by way of a default; and outputting an error signal if the determined value of the comparison signal does not correspond to the default.
申请公布号 US7409308(B2) 申请公布日期 2008.08.05
申请号 US20060469365 申请日期 2006.08.31
申请人 INFINEON TECHNOLOGIES AG 发明人 FRANKOWSKY GERD;MAYR ROMAN
分类号 G06F19/00 主分类号 G06F19/00
代理机构 代理人
主权项
地址