| 摘要 |
Disclosed is a digital filter with a combined architecture of a 4-tap real valued filter and a-tap complex valued filter, whereby the filter size is reduced and no output delay is occurred due to the filter operations. According to the present invention, the digital filter is operated either in real valued filter mode or complex valued filter mode according to a mode selection signal, a filter output is obtained within one clock according to an operation selection signal, and an operator performs operations twice within one symbol clock (i.e., a time period) unlike a related art filter in which an operator performs the operation only once for each symbol clock. Therefore, the present invention filter is capable of resolving the filter size problem by substantially reducing the number of multipliers and adders.
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