发明名称 |
Low-voltage single-layer polysilicon EEPROM memory cell |
摘要 |
The present invention is an electronic memory cell and a method for the cell's fabrication comprising a first transistor configured to be coupled to a bit line. The first transistor has an essentially zero voltage drop when activated and is configured to control an operation of the memory cell. A second transistor is configured to operate as a memory transistor and is coupled to the first transistor. The second transistor is further configured to be programmable with a voltage about equal to a voltage on the bit line.
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申请公布号 |
US7408812(B2) |
申请公布日期 |
2008.08.05 |
申请号 |
US20060548444 |
申请日期 |
2006.10.11 |
申请人 |
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发明人 |
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分类号 |
G11C11/34;H01L21/8238;H01L21/8247;H01L27/115;H01L29/78 |
主分类号 |
G11C11/34 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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