N+ poly on high-k dielectric for semiconductor devices

摘要

The present invention facilitates semiconductor fabrication by providing methods of fabrication that employ high-k dielectric layers. An n-type well region ( 304 ) is formed within a semiconductor body ( 302 ). A threshold voltage adjustment implant is performed by implanting a p-type dopant into the n-type well region to form a counter doped region ( 307 ). A high-k dielectric layer ( 308 ) is formed over the device ( 300 ). A polysilicon layer ( 310 ) is formed on the high-k dielectric layer and doped n-type. The high-k dielectric layer ( 308 ) and the polysilicon layer ( 310 ) are patterned to form polysilicon gate structures. P-type source/drain regions ( 306 ) are formed within the n-type well region ( 304 ).