| 摘要 |
Compression stress applying portions 20 of SiGe film are formed in the source/drain regions of the p-MOSA region 30 a. Then, impurities are implanted in the p-MOS region 30 a and the n-MOS region 30 b to form shallow junction regions 22 a , 22 b and deep junction regions 23 a , 23 b. The impurity in the shallow junction regions 22 a , 22 b is prevented from being diffused immediately below the gate insulation film 15 by the thermal processing in forming the SiGe film, the short channel effect is prevented, and the hole mobility of the channel region of the p-MOS transistor 14 a. The operation speed of the p-MOS transistor 13 a is balanced with that of the n-MOS transistor, whereby the operation speed of the complementary semiconductor device 10 can be increased. The semiconductor device fabricating method can increase and balance the operation speed of a p-transistor with that of an n-transistor.
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