发明名称 BIAS CIRCUIT
摘要 PROBLEM TO BE SOLVED: To reduce bias deviation in a case where a current increases during an FET active state. SOLUTION: In accordance with a gate voltage of the FET, a base potential of a transistor provided in parallel with a resistor for drain current detection is controlled. COPYRIGHT: (C)2008,JPO&INPIT
申请公布号 JP2008177987(A) 申请公布日期 2008.07.31
申请号 JP20070011215 申请日期 2007.01.22
申请人 NEC CORP 发明人 HIROSAKA SHIRO
分类号 H03F3/193;H03F3/24 主分类号 H03F3/193
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