发明名称 |
BONDING PAD FOR SEMICONDUCTOR INTEGRATED CIRCUIT, MANUFACTURING METHOD FOR THE BONDING PAD, SEMICONDUCTOR INTEGRATED CIRCUIT, AND ELECTRONIC EQUIPMENT |
摘要 |
<P>PROBLEM TO BE SOLVED: To provide a highly reliable bonding pad for a semiconductor integrated circuit which ensures the flatness of the surface of the pad, allows conduction of a sufficient amount of current, and shows less conduction failure on an opening path interconnecting metal wiring layers. <P>SOLUTION: The bonding pad 10 for the semiconductor integrated circuit includes the opening path P interconnecting the metal wiring layers. The opening path P is composed of a latticed pattern of opening portions having at least two different opening widths consisting of one opening width necessary for filling the opening path and another opening width larger than one opening width. <P>COPYRIGHT: (C)2008,JPO&INPIT |
申请公布号 |
JP2008177249(A) |
申请公布日期 |
2008.07.31 |
申请号 |
JP20070007492 |
申请日期 |
2007.01.16 |
申请人 |
SHARP CORP |
发明人 |
ISHIHARA KAZUYA;AWAYA NOBUYOSHI |
分类号 |
H01L21/3205;H01L21/60;H01L23/52 |
主分类号 |
H01L21/3205 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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