发明名称 |
METHOD OF EVALUATING SOI TRANSISTOR AND EVALUATION APPARATUS FOR SOI TRANSISTOR |
摘要 |
PROBLEM TO BE SOLVED: To provide an evaluation method which allows a precise measurement of the effective parasitic capacity when SOI-MOSFET is operated on AC, a quality evaluation method for an SOI substrate after MOSFET formation, and an evaluation apparatus for these methods. SOLUTION: An AC signal is superimposed on the gate bias of the SOI-MOSFET, and the effective parasitic capacity is measured from the response of drain current using a lock-in amplifier. By measuring the effective parasitic capacity under different conditions of the back gate bias and the sample temperature of the SOI-MOSFET and then comparing the measurement results, the quality of the interface between an SOI layer and a buried oxide film (BOX layer) can be evaluated. COPYRIGHT: (C)2008,JPO&INPIT
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申请公布号 |
JP2008177333(A) |
申请公布日期 |
2008.07.31 |
申请号 |
JP20070008969 |
申请日期 |
2007.01.18 |
申请人 |
INSTITUTE OF NATIONAL COLLEGES OF TECHNOLOGY JAPAN |
发明人 |
HAYAMA KIYOTERU;OYAMA HIDENORI;TAKAKURA KENICHIRO |
分类号 |
H01L29/786;G01R31/26;H01L27/12 |
主分类号 |
H01L29/786 |
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地址 |
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