| 摘要 |
PROBLEM TO BE SOLVED: To shorten a period of time needed for AD conversion by decreasing the number of clocks needed for the AD conversion. SOLUTION: A staircase waveform having steps as many as 2 raised to (K)th power is generated as a voltage waveform of a course DAC for a high-order bit reference signal. A comparator 1 compares the course DAC with a vertical signal line level in an auto-zero state and an up/down counter 117 counts up high-order bits and stops counting them when the potential of the course DAC becomes lower than that of a vertical signal line; and a Tr 21 is turned off based upon a comparator output and the potential difference Vof between a fine DAC and the course DAC is held in a Cp 25. Then the fine DAC is varied in steps of 2 raised to (L)th power to make a comparison with the comparator, and the up/down counter 117 counts down starting at a stop value of a high-order bit count for a period of the fine DAC. Consequently, the time needed for single-time AD conversion corresponding to a resolution of J bits of an AD converter is obtained by voltage comparison (J=K+L) made as many as (2 raised to (K)th power plus 2) raised to (L)th power. COPYRIGHT: (C)2008,JPO&INPIT
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