| 摘要 |
PROBLEM TO BE SOLVED: To enable high-speed operation in less circuit resources by employing a circuit configuration and a process system suitable for the function expansion of a FPGA (field programmable gate array) in an encryption circuit processing encryption algorithm by remainder operation, and moreover, to enhance versatility of the circuit. SOLUTION: A Montgomery multiplication circuit 201 carries out remainder operation by Montgomery multiplication based on an addition of the multiplication result of A and B, the multiplication result of M and Q, and an intermediate result S, wherein A is the multiplicand, B is the multiplier, M is the modulus, and Q is the intermediate value. In the circuit, an operation circuit A301 and an operation circuit D601 carry out the multiplication of A and B and the multiplication of M and Q at an operational frequency clk2x which is twice a predetermined operational frequency clk1x; and an operation circuit B401 and operation circuit C501 carry out the addition of the above two multiplication results with S at the frequency clk1x. The operation circuit C501 carries out remainder operation by Montgomery multiplication based on the result of addition. COPYRIGHT: (C)2008,JPO&INPIT
|
