| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory using a hierarchical bit line system for reducing an area. <P>SOLUTION: The semiconductor memory includes: a plurality of local bit lines LBL for selecting a row of each memory cell array 11; a plurality of local sense amplifiers 12, each of which is arranged in each of two memory cell arrays 11 and detects data to be transferred from the memory cell via each local bit line LBL; a plurality of replica cell groups 15 arranged in response to the plurality of local sense amplifiers 12; a plurality of replica bit lines RBL respectively connected to the plurality of replica cell groups 15; a plurality of active circuits 14 for activating the local sense amplifiers 12, based on the potential of the replica bit lines RBL; and a contact region 17 where contacts for supplying power to the well region of a transistor constituting memory cells are arranged. The two memory cell arrays 11 connected to the different local sense amplifiers 12 are adjacently arranged without holding the contact region 17 between them. <P>COPYRIGHT: (C)2008,JPO&INPIT |
