发明名称 TIMING VERIFICATION METHOD AND TIMING VERIFICATION DEVICE
摘要 PROBLEM TO BE SOLVED: To provide a timing verification method, capable of performing accurate timing verification according to a wiring structure of a semiconductor integrated circuit device. SOLUTION: The method comprises a coefficient calculation process provided with a first storage means for storing, for wiring of a standard shape, a table of wiring resistance dispersion and wiring capacity dispersion according to the shape of the wiring for extracting a wiring structure in a signal path, extracting the wiring resistance dispersion and wiring capacity dispersion according to the wiring structure from the table, and obtaining a coefficient from the wiring resistance dispersion and wiring capacity dispersion extracted from the table. A delay time of signal propagation in the signal path is determined based on the coefficient. COPYRIGHT: (C)2008,JPO&INPIT
申请公布号 JP2008176628(A) 申请公布日期 2008.07.31
申请号 JP20070010361 申请日期 2007.01.19
申请人 FUJITSU LTD 发明人 AKAMINE TAKEICHIRO;HOSONO TOSHIKATSU
分类号 G06F17/50 主分类号 G06F17/50
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