发明名称 TIMING VERIFICATION METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To highly precisely perform timing verification by increasing the calculating precision of cell delay and wiring delay changing according to a local temperature difference. SOLUTION: This timing verification method includes a power consumption calculation process S1 for calculating the power consumption P of a semiconductor circuit for every instance; a driving cell temperature calculation process S2 for calculating the temperature T of each instance from power consumption; a wiring resistance temperature correction process S3 for setting the temperature of each instance as the temperature of wiring to be driven by the instance, and for calculating the wiring resistance of the change of temperature with respect to wiring to be driven by the instance from the temperature and first parasitic element information K1 in which the wiring resistance and wiring capacity of the semiconductor circuit are written, and for outputting second parasitic element information K2; a delay calculation process S4 for calculating a cell delay time and wiring delay time on which the wiring resistance changing according to the local temperature difference is reflected from the second parasitic element information K2 and a delay library L; and a timing verification process S5 for verifying a timing based on the delay time. COPYRIGHT: (C)2008,JPO&INPIT
申请公布号 JP2008176450(A) 申请公布日期 2008.07.31
申请号 JP20070007841 申请日期 2007.01.17
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 HIRATA MASAAKI;YAMAGUCHI RYUICHI
分类号 G06F17/50;H01L21/82 主分类号 G06F17/50
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