发明名称 TEST CIRCUIT AND TEST METHOD OF ERROR DETECTION CORRECTING CIRCUIT
摘要 <P>PROBLEM TO BE SOLVED: To test an ECC circuit of a memory by less additional circuits. <P>SOLUTION: After initial data and parity bits formed by a parity bit developing circuit 300 based on the initial data are written into a data memory 200 and a parity bit memory 400, data having a single-bit value different from that of the initial data are controlled so as to write into the data memory 200 only, and error is corrected in the error detection correcting circuit 500 by using the parity bit based on the initial data at the read-out of memory, then the ECC circuit is tested by comparing the error correction read-out data and the initial data. <P>COPYRIGHT: (C)2008,JPO&INPIT
申请公布号 JP2008176828(A) 申请公布日期 2008.07.31
申请号 JP20070007105 申请日期 2007.01.16
申请人 TOSHIBA MICROELECTRONICS CORP;TOSHIBA CORP 发明人 OSHIMA MAMORU
分类号 G11C29/42;G01R31/28;G06F12/16 主分类号 G11C29/42
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