发明名称 |
COLUMN REDUNDANCY CIRCUIT WITH REDUCED SIGNAL PATH DELAY |
摘要 |
The invention discloses a synchronous DRAM having memory elements arranged in rows and columns, the memory elements being accessible by decoding a memory address applied thereto, normal column drivers for activating appropriate memory elements in response to decoded column addresses signals; redundant column drivers distributed throughout memory banks and flexibly selectable to replace faulty columns within multiple blocks within a bank; and switch means for selectively activating the redundant column and preventing the activation of a defective normal column, whereby the column redundancy method and apparatus minimizes the timing difference between a normal and redundant column paths and which minimizes the number of fuses required to be blown in repairing faulty columns addresses.
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申请公布号 |
CA2347765(C) |
申请公布日期 |
2008.07.29 |
申请号 |
CA19992347765 |
申请日期 |
1999.10.29 |
申请人 |
MOSAID TECHNOLOGIES INCORPORATED;MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. |
发明人 |
KIKUKAWA, HIROHITO;WEI, FANGXING;MAR, CYNTHIA |
分类号 |
G11C8/08;G11C11/401;G06F11/20;G11C7/12;G11C11/4193;G11C29/00;G11C29/04 |
主分类号 |
G11C8/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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