| 摘要 |
A test pattern generation circuit having a plurality of pseudo random number generation circuits respectively receiving a clock signal at different timing is provided to perform feedback test having a high test coverage by improving randomness in a data sequence direction and the randomness of combination of data pieces in a data width direction. A plurality of pseudo random number generating circuits(13_1-13_n) correspond to each signal line of bus wiring, respectively have a first initial value preset to have the same value, and generates a pseudo random number having the first initial value as a starting value by responding to a first clock signal. A clock control circuit(11) determines timing for starting output of the first clock signal provided to each pseudo random number generation circuit depending on the value of a control signal, which is the first clock signal. The clock control signal includes a first clock control circuit(12) receiving a reference clock as an input signal and setting a shift amount at the timing for starting supplying the first clock signal to the pseudo random number generation circuits depending on the value of the control signal.
|
