发明名称 |
Combination of non-lithographic shrink techniques and trim process for gate formation and line-edge roughness reduction |
摘要 |
The present invention relates generally to photolithographic systems and methods, and more particularly to systems and methodologies that facilitate the reduction of line-edge roughness (LER) during gate formation in an integrated circuit. Systems and methods are disclosed for improving critical dimension (CD) of photoresist lines, comprising a non-lithographic shrink component that facilitates mitigating LER, and a trim etch component that facilitates achieving and/or restoring a target critical dimension.
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申请公布号 |
US7405032(B1) |
申请公布日期 |
2008.07.29 |
申请号 |
US20030645364 |
申请日期 |
2003.08.21 |
申请人 |
ADVANCED MICRO DEVICES, INC. |
发明人 |
AMBLARD GILLES;DAKSHINA-MURTHY SRIKANTESWARA;SINGH BHANWAR |
分类号 |
G01B11/30;G01B11/00;G03C5/00 |
主分类号 |
G01B11/30 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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