发明名称 DLL CIRCUIT AND METHOD FOR CONTROLLING THE SAME
摘要 <p>A delay locked loop circuit and a method for controlling the same are provided to output a clock of which a duty ratio is not changed by a PVT(Process, Voltage, Temperature) change. A delay locked loop circuit includes a duty ratio detection unit(60), a correction control unit(20), and a duty ratio correction unit(30). The duty ratio detection unit detects a duty ratio of a rising clock and a duty ratio of a falling clock, and outputs a duty ratio detection signal. The correction control unit generates a correction control signal in response to the duty ratio detection signal. The duty ratio correction unit corrects a duty ratio of an internal clock in response to the correction control signal, and outputs a reference clock. The duty ratio detection unit determines the duty ratio of the rising clock and the duty ratio of the falling clock and generates the duty ratio detection signal by comparing a second edge of the rising clock with a second edge of the falling clock after a first edge of the rising clock is consistent with a first edge of the falling clock.</p>
申请公布号 KR20080069756(A) 申请公布日期 2008.07.29
申请号 KR20070007371 申请日期 2007.01.24
申请人 HYNIX SEMICONDUCTOR INC. 发明人 SHIN, DONG SUK;LEE, HYUN WOO;YUN, WON JOO
分类号 H03L7/00;G11C11/4076;H03K5/04;H03L7/081;H03L7/087 主分类号 H03L7/00
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