| 摘要 |
This invention discloses a semiconductor test structure array comprising a plurality of unit cells for containing devices under test (DUT) arranged in an addressable array, and an access-control circuitry within each unit cell for controlling accesses to one or more DUTs, wherein the access-control circuitry comprises at least four identical controlled transmission gates (CTGs), and a plurality of the access-control circuitries are isomorphic.
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