发明名称 |
Technique for switching between input clocks in a phase-locked loop |
摘要 |
A technique that is readily implemented in monolithic integrated circuits reduces or eliminates phase glitches when switching between input reference clock signals. The technique combines a pulsed phase-difference signal and a pulsed phase-difference compensation signal to substantially attenuate a DC component of the phase-difference signal and at least partially attenuate harmonic components of the phase-difference signal. The pulsed phase-difference compensation signal is based on an indicator of a phase difference between the input reference clock signals.
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申请公布号 |
US7405628(B2) |
申请公布日期 |
2008.07.29 |
申请号 |
US20060537082 |
申请日期 |
2006.09.29 |
申请人 |
SILICON LABORATORIES INC. |
发明人 |
HULFACHOR RONALD B.;SEETHAMRAJU SRISAI R.;CHITNIS SHAILESH |
分类号 |
H03L7/00 |
主分类号 |
H03L7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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