| 摘要 |
A device and a method for controlling timing for transiting an SDA(Serial DAta line) in an I2C(Inter-IC) controller are provided to prevent incorrect operation in I2C communication in a simple way not using a compensation circuit requiring lots of time/cost by enabling the I2C controller to control the timing for transiting the SDA. An SCL(Serial Clock Line) edge detector(404) detects an edge of a clock signal in an SCL. A counter(406) counts a hold time of a status of an SDA when a falling edge of the clock signal is detected by the SCL edge detector. An SDA generator(408) transits the SDA when counting the hold time is finished. A processor(402) interfaces the SCL edge detector, the counter, and the SDA generator. An I2C slave interface sets the hold time to the counter by receiving the hold time from a CPU. The processor determines whether the SDA is transited for transferring a data transfer start or finish signal, or transferring data. The SDA generator transits the SDA without counting the hold time when the SDA is transited for transferring the data transfer start or finish signal.
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