发明名称 |
Structure of test area for a semiconductor tester |
摘要 |
Devices and methods for DC and SLT (system level test) integration are disclosed. The DC circuit and the SLT circuit are integrated into the same device. Therefore, the DUT (device under testing) can precede the SLT before the FT (final test) when the DUT passes the DC.
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申请公布号 |
US2008174331(A1) |
申请公布日期 |
2008.07.24 |
申请号 |
US20070819084 |
申请日期 |
2007.06.25 |
申请人 |
KING YUAN ELECTRONICS CO., LTD. |
发明人 |
YUAN-CHI LIN;HSIEH CHIH-HUNG;LIN SHIH-FANG;PAN HAO-HSIN |
分类号 |
G01R31/26 |
主分类号 |
G01R31/26 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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