| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a frequency synthesizer capable of realizing frequency division of high precision while suppressing circuit increase, without using a PLL of a conventional configuration, and to provide a clock generation method. <P>SOLUTION: The frequency synthesizer comprises phase selection synthesizers 502 and 503 for generating a clock of a plurality of frequencies based on a N phase clock from a reference clock generator 501. At a clock selecting means 504 in the phase selection synthesizers 502 and 503, a clock of (N/M)f is generated by inputting the N phase clock and a phase number (j: integral number from 0 to (N-1)) and selecting a clock corresponding to the phase number. At a phase number generation means 505, the clock of (N/M)f, a division denominator M, and a division numerator N are inputted, and a value (M-N) synchronized with the clock of (N/M)f and computed from the division denominator M and the division numerator N is totaled. Then, a remainder from division of the totaled value ACC by N is adopted as the phase number (j). <P>COPYRIGHT: (C)2008,JPO&INPIT |
