| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device which is advantageous to EM and ESD. <P>SOLUTION: There are provided a plurality of I/O cells (17), a power source wiring formed of a plurality of wiring layers on the I/O cell, a bonding pad (11) formed at the position corresponding to the I/O cell, in the layer above the power source wiring, and draw-out regions (31 and 32) which allow the I/O cell to electrically connect to the bonding pad. The power source wiring comprises a first power source wiring (15) and a second power source wiring (16). The I/O cell comprises first elements (D1 and QP1) connected to the first power source wiring, and second elements (D2 and QN1) connected to the second power source wiring. The first element is arranged on the first power source wiring side, and the second element is arranged on the second power source wiring side. The first power source wiring and the second power source wiring tolerate a large current thanks to the plurality of wiring layers on the I/O cell, so that they are advantageous to EM and ESD. <P>COPYRIGHT: (C)2008,JPO&INPIT |
