| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To reduce the manufacturing cost per megabyte of a memory for a fraction of the cost for conventionally manufacturing, merely by a monolithic circuit integration method. <P>SOLUTION: A three-dimensional structure (3DS) memory (100) allows for the physical separation of the memory circuits (103) and the control logic circuit (101) onto different layers, such that each layer is separately optimized. One control logic circuit (101) is sufficient for several memory circuits (103), and cost can be reduced. Fabrication of 3DS memory (100) includes a step of thinning of the memory circuit (103) to smaller than 50μm in thickness, and a step of bonding the memory circuit to a circuit stack, while still in wafer substrate form. Fine-grain high density interlayer vertical bus connections (105) are used. The 3DS memory (100) manufacturing method enables several performance and physical size efficiencies and is implemented with established semiconductor processing techniques. <P>COPYRIGHT: (C)2008,JPO&INPIT</p> |
